1. Field of the Invention
This invention relates generally to the fabrication and precision alignment of an array of semiconductive chips, and more particularly to an improved method of aligning such an array when assembled into a printing subsystem.
2. Description of the Prior Art
Fabrication of pagewidth silicon devices from sub-units, such as image sensor arrays having photosites and supporting circuitry integrated onto a silicon substrate and thermal ink jet printheads having an etched silicon structure mated and bonded to a silicon substrate with heating elements and addressing electrodes, impose economically difficult fabricating processes on manufacturers because of the close tolerance requirement for the abutting edges of side-by-side sub-units assembled to produce the pagewidth devices. Furthermore, once such arrays are fabricated to close tolerances, they must be aligned within the larger apparatus and/or with respect to additional arrays within the apparatus. For example, in a multicolor printing system, having a plurality of single color ink jet printhead arrays, the individual arrays must be aligned to produce the desired spacing for respective colored ink dots which are deposited on an output sheet.
Although the standard technique of dicing or scribing and cleaving silicon wafers used by the semiconductive industry produces silicon devices or chips having reasonably controlled dimensions, the microscopic damage occurring to the chip surface during the scribing or dicing operation has effectively precluded the deposition of circuitry or photosites at the chip edge. This has necessitated that a safe distance be maintained. between the last circuit element or photosite and chip edges, if operation of these adjacent photosites or ink jet circuitry is not to be impaired by the presence of either microcracks or silicon chipping along the cleaved or diced edges. Moreover, once the devices or chips are assembled into an array and affixed to a support member, there is no assurance that required dimensional tolerances with respect to positioning of the array will be met.
U.S. Pat. No. 4,851,371 to Fisher et al., discloses a fabrication process for large area semiconductor devices. A pagewidth printing device may be assembled by abutting silicon device sub-units comprising a channel plate and a heater plate which are bonded together. Prior to bonding the channel plate to the heater plate, the channel plate is formed having a trapezoidal shape by etching elongated slots into the plate. After bonding, the heater plates are diced to form kerfs having vertical to inwardly directed sides which enable high tolerance linear abutment.
U.S. Pat. No. 4,822,755 to Hawkins, et al., discloses a method of fabricating large area semiconductor arrays and a method of separating chips formed on a silicon substrate which uses reactive ion etching techniques combined with orientation etching to make integrated chips which may be precisely butted to form a large array. Chip separation is accomplished by dice cutting along a back of the heater plate.
U.S. Pat. No. 4,814,296 to Jedlicka et al, discloses a method of fabricating image sensor dies for use in scanning arrays. V-shaped grooves are etched on the active side of the wafer prior to sawing to prevent cracking and chipping due to sawing.
U.S. Pat. Nos. 4,690,391 and 4,712,018 to Stoffel et al. disclose methods and apparatus for fabricating long, full width scanning arrays by assembling smaller scanning arrays in abutting end-to-end relation. An aligning tool, having predisposed pins, is used to mate a series of smaller arrays in the abutting relationship. FIGS. 3 and 4 of both patents, illustrate the arrays 10, aligning tool 25 and aligning pins 30 thereon which are used to mate with V-shaped aligning grooves in the arrays, thereby enabling alignment of the arrays.
U.S. Pat. No. 4,829,324 to Drake et al., discloses a large array ink jet printhead having two parts, the first having heating elements and addressing electrodes on the surface thereof. The second part containing the liquid ink handling system. The two parts are formed on distinct wafers, with at least the second part being formed on a silicon wafer. The two wafers, having the described features thereon, are aligned and bonded together, then diced into complete printhead sub-units which have abutting side surfaces that are {111} planes for accurate side-by-side assembly.
U.S. Pat. No. 4,929,300 to Wegleiter discloses a process for separating LED chip arrangements fabricated on a substrate wafer so that they can be arrayed in a series with other LED chips. Chips are separated from the wafer by etching a depression in the back side of each chip prior to double saw cutting the chips to produce chips which can be precisely aligned, as illustrated in FIG. 1.
Thermal ink jet printing systems use thermal energy selectively produced by resistors located in capillary filled ink channels near channel terminating nozzles or orifices to momentarily vaporize the ink and form bubbles on demand. Each temporary bubble expels an ink droplet and propels it towards a recording medium. The printing system may be incorporated in a pagewidth type printer, as disclosed in U.S. Pat. No. 4,463,359 to Ayata et al., which teaches printhead having one or more ink filled channels which are replenished by capillary action. A meniscus is formed at each nozzle to prevent ink from weeping therefrom. A resistor or heater is located in each channel upstream from the nozzles. Current pulses representative of data signals are applied to the resistors to momentarily vaporize the ink in contact therewith and form a bubble for each current pulse. Ink droplets are expelled from each nozzle by the growth of the bubbles which cause a quantity of ink to bulge from the nozzle and break off into a droplet at the beginning of the bubble collapse. The current pulses are shaped to prevent the meniscus from breaking up and receding too far into the channels, after each droplet is expelled. Various embodiments of linear arrays of thermal ink jet devices are shown, such as those having staggered linear arrays attached to the top and bottom of a heat sinking substrate for the purpose of obtaining a pagewidth printhead. Such arrangements may also be used for different colored inks to enable multi-colored printing.
Furthermore, U.S. Pat. No. 4,774,530 to Hawkins, discloses the use of an etched thick film insulative layer to provide the flow path between the ink channels and the manifold, and U.S. Pat. No. 4,786,357 to Campanelli et al., discloses the use of an etched thick film insulative layer between mated and bonded substrates. One substrate has a plurality of heating element arrays and addressing electrodes formed on the surface thereof and the other is a silicon wafer having a plurality of etched manifolds, with each manifold having a set of ink channels. The etched thick film layer provides a clearance space above each set of contact pads of the addressing electrodes to enable the removal of the unwanted silicon material of the wafer by dicing without the need for etched recesses therein. The individual printheads are produced subsequently by dicing the substrate having the heating element arrays.
Drop-on-demand thermal ink jet printheads discussed in the above patents are generally fabricated using silicon wafers and processing technology to make multiple small heater plates and channel plates. This works extremely well for small printheads. The fabrication approaches for making either large array or pagewidth thermal ink jet printheads can be divided into basically two broad categories; namely, monolithic approaches in which one or both of the printhead components (heater substrate and channel plate substrate) are a single large array of pagewidth size, or sub-unit approaches in which smaller sub-units are combined to form the large array or pagewidth print bar. For examples of the sub-unit approach, refer to U.S. Pat. No. 4,829,324 to Drake et al. The sub-units approach results in a much higher yield of usable sub-units, if they can be precisely aligned with respect to one another. The assembly of a plurality of sub-units, however, require precise individual registration in both the x-y-z planes as well as the registration of the assembled array in the x-y-z planes. The alignment problems for these assembled arrays presents quite a formidable task, and one which has, up to this point, required expensive alignment mechanisms and techniques.